A major driving force in semiconductor technology is the integration of a larger electrical circuitry system into a single chip. There exist two general ways to achieve this goal including: 1) reducing the minimum feature size and 2) increasing the die size.
The pursuit of the goal to integrate a larger system within a single chip has resulted in numerous advancements. In particular, the aim to reduce the minimum feature size has led to the introduction of 0.35 micron technology in production. Further, the semiconductor industry is aggressively pursuing development of 0.25 micron and 0.18 micron technologies.
The goal of increasing die size has led to an increase in chip size. Currently, 450 mm.sup.2 chips are produced and the size is projected to increase to 750 mm.sup.2 by the year 2001.
The progress in both approaches identified above is today fundamentally dependent upon photolithographic capabilities. The method of reducing minimum feature size is determined by the resolution capability of the photolithography equipment. The method of increasing die size is limited by the field size of the photolithography equipment being utilized.
In particular, the maximum die size is limited by the stepper field size. The stepper field size is the circular field defined by the photolithography equipment optics. The physical laws governing optics mandate circular stepper fields.
FIG. 1 shows a semiconductor wafer 4 having an array 6 of conventional square dies 8 formed thereon. The portions of the substrate intermediate the perimeter of the semiconductor wafer 10 and the array 6 are often not utilized which results in a considerable amount of waste of expensive semiconductor materials.
The present invention is drawn towards providing an optimized die shape to maximize the die size for any particular photolithography capability.